Semiconductor memory devices of flash memory and the like conventionally have been constructed by two-dimensionally integrating memory cells on the surface of a silicon substrate. In such a semiconductor memory device, it is necessary to increase the integration of the memory cells to reduce the cost per bit and increase the storage capacity. However, such increases of integration in recent years have become difficult in regard to both cost and technology.
Methods of three-dimensional integration by stacking memory cells have been proposed as technology to breakthrough the limitations of increasing the integration. However, methods that simply stack and pattern one layer after another undesirably increase the number of processes as the number of stacks increases, and the costs undesirably increase. In particular, the increase of lithography processes for patterning the transistor structure is a main cause of increasing costs. Therefore, the reduction of the chip surface area per bit by stacking has not led to lower costs per bit as much as downsizing within the chip plane and is problematic as a method for increasing the storage capacity.
In consideration of such problems, the inventors have proposed a collectively patterned three-dimensionally stacked memory (for instance, refer to JP-A 2007-266143 (Kokai)). In such technology, a stacked body including electrode films alternately stacked with insulating films is formed on a silicon substrate; and subsequently, through-holes are made in the stacked body by collective patterning. A blocking film, a charge storage film, and a tunneling film are deposited in this order to form a memory film on the side face of the through-hole; and a silicon pillar is buried in the interior of the through-hole. A memory transistor is thereby formed at an intersection between each electrode film and the silicon pillar.
In such a collectively patterned three-dimensionally stacked memory, a charge can be removed from and put into the charge storage layer from the silicon pillar to store information by controlling an electrical potential of each electrode film and each silicon pillar. According to such technology, the through-holes are made by collectively patterning the stacked body. Therefore, the number of lithography processes does not increase and cost increases can be suppressed even in the case where the number of stacks of the electrode films increases.